1. Technical Field
The present invention relates to mechanisms for processing digital data, and in particular to mechanisms for combining signals to provide consistent output behavior.
2. Background Art
Digital systems often include circuitry that combines two or more signals to generate a new signal. For example, some communication systems encode data using pulse width modulation (PWM) to represent one or more bits of data in the width of an electronic pulse. One way to produce such a pulse is to generate a first signal that initiates the pulse and, at a delay determined by the states of one or more bits, to generate a second signal that terminates the pulse. The initiating and terminating signals (xe2x80x9cprogramming signalsxe2x80x9d) may be signal transitions such as the leading or trailing edges of pulses.
Because data is encoded in the pulse width, the initiating and terminating signals should generate data pulses with reproducible widths. Ideally, the width of the output pulse depends on only selected properties of the programming signals, and is substantially independent of other properties of the programming signals. For example, where the selected properties are the leading edges of the programming signals, the resulting pulse should be substantially independent of the width of either programming signal. Known circuits for combining signals to generate a new signal do not guarantee this independence.
FIG. 1 is a schematic diagram of an edge-to-pulse converter or generator 100. A pre-charge transistor 110 is connected in series with transistors 120 and 130, which perform an AND function for initiating and terminating signals. For the disclosed circuit, START is an initiating signal that is asserted when it is in a high voltage state, and_STOP is a terminating signal that is asserted when it is in a low voltage state. Pre-charge transistor 110 initializes node N to a high voltage state when_STOP is low (asserted). An inverter 140 converts the high voltage at node N to a low voltage state at output 142. When_STOP goes high, i.e. when the terminating signal is not asserted, N remains in the high voltage state as long as START is not asserted, and output 142 remains in the low voltage state. Converter 100 may be initialized by this sequence of signals.
With_STOP deasserted, an output pulse (O_PULSE) is initiated by asserting START. Node N discharges through transistors 120 and 130, driving output 142 to a high voltage state. In this state, node N is exposed to a parasitic capacitance at intermediate node M, between transistors 120 and 130. The parasitic capacitance is indicated by capacitor 150. When_STOP is asserted, i.e. driven low, the path to ground through transistor 130 is cut off. Node N is recharged to a high voltage state through transistor 110 and output 142 goes low, terminating O_PULSE.
Depending on its width, START may or may not still be asserted when_STOP is asserted. As a result, transistor 120 may be open or closed, and node N may or may not be exposed to parasitic capacitance 150 when O_PULSE is terminated. The difference in the capacitance seen by transistor 110 can alter the width of O_PULSE generated at output 142. For example, it may cause variations in the trailing edge of O_PULSE, providing, in effect, unintended modulation of its pulse width. Unintended width modulations can have significant consequences for data integrity, particularly at higher frequencies. For example, if these variations are significant compared to the differences between pulse widths representing different bit states, data can be corrupted.
The edge-to-pulse converter discussed above demonstrates a particular example of a more common problem that arises whenever signals are combined to generate an output. That is, the output may depend on properties of the signals to be combined in ways that are not desired.
The present invention addresses these and other problems associated with combining signals to generate an output.